CVI is available to assist with Pb-free solutions
and qualification on devices, packages and boards. Our team consists of board layout, packaging and an SMT team to help in
all facets of development.
Our goal is to assist the customer
with the proper analysis tools (DOE/FMEA) to reduce development time and cost. The CVI team will assure the correct
materials are chosen for sockets, solder bumps, and test probes.
Advanced Packaging Solutions
- Chip Scale Packages
- Root Cause Analysis
- Design and Development
- Optical and Standard Packages
- Multiple Die and Stacked Packages
- Cleaning and Contamination Removal
- Board Layout and Design
- RDL design and analysis
Why CVInc Solder Bumping
- •2-3
day cycle time possible
-
•Smallest
bump to date is 25um bump with 36um pitch
-
•Bump/Ball
size from 25um to 1mm.
-
•SMT
equipment for board assembly and removal
-
•Forming gas or flux assembly
-
CVInc can remove oxide to reflow without
forming gas or flux in vacuum
-
Numerous alloys including In, high Pb, AuSn
and many Sn based alloys
-
•RDL
capability on complete and partial wafers
-
Read
the following article to understand how voiding, IMC formation and MSD might impact performance. (solder ball endurance - click here)
